1. Field of the Invention
The present invention relates to analog-to-digital converting circuitry which can accept an analog signal and produce an n-bit (n is an integer which is greater than or equal to 2) digital signal which represents the analog signal and, more particularly, to successive approximation analog-to-digital converting circuitry for successively analog-to-digital converting the value of an analog input signal being held therein into a digital signal bit-by-bit in synchronization with a clock signal applied thereto.
2. Description of the Prior Art
Improvements have been made in order to speed up the analog-to-digital converting operation of a prior art analog-to-digital converter which can accept an analog signal and produce an n-bit (n is an integer which is greater than or equal to 2) digital signal which represents the analog signal. For example, in Japanese Patent Application Laying Open (KOKAI) No. 60-211533, there is disclosed an Analog-to-digital converter comprising a plurality of sample-and-hold circuits each for sampling and holding an analog input signal, a plurality of Analog-to-digital converting circuits each analog-to-digital converting an output signal from each of the plurality of sample-and-hold circuits, a selecting unit for selecting one from among outputs from the plurality of Analog-to-digital converting circuits to output the selected one, and a control circuit for controlling the operation timing of each of the circuits included in the Analog-to-digital converter. The Analog-to-digital converter starts a sequence of analog-to-digital converting operations in response to a hold instruction at predetermined intervals of T1 which is longer than the length of time T required for a set of a sampling and holding operation, an analog-to-digital converting operation, and an operation of furnishing the binary word which are repeated as a unit. A plurality of sample-and-hold instructions are sequentially delivered to the plurality of sample-and-hold circuits at predetermined intervals of T1/n, respectively. That is, the plurality of sample-and-hold instructions are shifted from each other in time by the length of time T1/n. As a result, the maximum sampling rate becomes (n/T). Thus the analog-to-digital conversion processing can be speeded up.
Japanese Patent Application Laying Open (KOKAI) No. 2-105629 discloses an Analog-to-digital converting apparatus comprising an analog multiplexer for furnishing an analog input signal applied thereto to a plurality of destinations by turns, a plurality of sample-and-hold circuits connected to the analog multiplexer, each for sampling and holding the analog input signal from the analog multiplexer, a plurality of Analog-to-digital converters each for analog-to-digital converting the analog input signal into a digital signal, a digital multiplexer for selecting one from among outputs from the plurality of Analog-to-digital converters and for furnishing the selected one, and a controller for controlling the analog multiplexer, the plurality of sample-and-hold circuits, the plurality of Analog-to-digital converters, and the digital multiplexer. By causing the analog multiplexer to deliver the analog input signal to the plurality of sample-and-hold circuits by turns, the Analog-to-digital converting apparatus disclosed in the reference can sample and hold the analog input signal at predetermined intervals of (1/n) of the minimum Ts of a conversion time period during which each of the plurality of Analog-to-digital converters can perform an Analog-to-digital converting operation, by means of the plurality of sample-and-hold circuits, and then analog-to-digital converts the analog input signal by means of the plurality of Analog-to-digital converters. Thus the Analog-to-digital converting apparatus offers a several-hold or tens-hold improvement in the Analog-to-digital conversion rate in accordance with the number of the plurality of Analog-to-digital converters included in the Analog-to-digital converting apparatus.
Japanese Patent Application Laying Open (KOKAI) No. 4-72919 discloses an analog-to-digital converting apparatus comprising a plurality of Analog-to-digital converters each for converting an analog signal into a digital signal, a sample clock generating unit for generating a plurality of sample clocks which are 180.degree. out of phase with each other and for furnishing the plurality of sample clocks to the plurality of Analog-to-digital converters, respectively, and a switching unit for selecting one from among outputs from the plurality of Analog-to-digital converters by turns and then sequentially furnishing the selected one in synchronization with each of the plurality of sample clocks from the sample clock generating unit. Thus the Analog-to-digital converting apparatus disclosed in the reference can speed up the Analog-to-digital conversion processing by respectively applying the plurality of sample clocks which are out of phase with each other by the same length of time to the plurality of Analog-to-digital converters by means of the sample clock generating unit, and then selecting outputs from the plurality of Analog-to-digital converters by turns and sequentially furnishing the outputs.
Japanese Patent Application Laying Open (KOKAI) No. 6-46010 discloses an analog-to-digital converting apparatus which can analog-to-digital converts an input signal in response to each of eight clock signals which are out of phase with each other. Each of eight Analog-to-digital converters included in the Analog-to-digital converting apparatus can quantize the input signal to an 8-bit digital word in response to each clock generate, so that the eight Analog-to-digital converters sequentially convert values of the input signal applied to the Analog-to-digital converting apparatus via one channel into eight 8-bit digital signals and send out them on eight sets of eight signal lines, respectively. Accordingly, the Analog-to-digital converting apparatus disclosed in the abovementioned reference can speed up the Analog-to-digital conversion processing.
Japanese Patent Application Laying Open (KOKAI) No. 7-162310 (U.S. Pat. No. 5,450,085) discloses a flash-type (i.e., full parallel-type) analog-to-digital converting apparatus comprising a voltage dividing network comprised of a plurality of resistors, for generating a plurality of reference voltages, first and second comparator banks each including a plurality of comparators each having its first input for receiving an analog signal, and its second input for receiving a reference voltage from the voltage dividing network, a comparator activating circuit for activating the comparators of the first comparator bank in response to an even-numbered pulse of a clock signal having two times as long as the periodicity of a system clock, and for activating the comparators of the second comparator bank in response to an odd-numbered pulse of the clock signal, and a digital output selector/encoder for coding outputs from the first and second comparator banks into two digital data, respectively, and then furnishing the two digital data selectively and sequentially. Thus the flash-type analog-to-digital converting apparatus disclosed in the reference can offer a two-fold improvement in the Analog-to-digital conversion rate by alternately activating the first and second comparator banks in response to even-numbered and odd-numbered pulses of the clock signal having two times as long as the periodicity of a system clock. The above-mentioned reference also discloses the use of n comparator banks.
In above-mentioned references such as Japanese Patent Application Laying Open No. 60-211533, No. 2-105629, No. 4-72919, and No. 6-46010, there is no description about the concrete structure of one Analog-to-digital converter included in the Analog-to-digital converting apparatus. However, it is assumed from information described in those references that each Analog-to-digital converter is in the form of a flash-type (i.e., full parallel-type) analog-to-digital converter including a plurality of comparison circuits each for comparing a reference voltage to the value of an analog signal at the same time that the other comparison circuits do, and an encoder for converting the comparison result into a digital signal and then furnishing the digital signal.
While such a prior art analog-to-digital converting apparatus using a plurality of flash-type (or full parallel-type) analog-to-digital converters as disclosed in the above-mentioned references can reduce the time required to convert the value of an analog input signal at a time into a digital signal, it has a disadvantage in that in order to generate an n-bit (n is an integer which is greater than or equal to 2) digital signal, (2.sup.n -1) comparison circuits are needed and therefore the size of the analog-to-digital converting circuitry increases with an increase in the number of bits of the n-bit digital signal to be generated.